R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1076

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 Stream Interface (STIF)
Rev. 2.00 May 22, 2009 Page 1006 of 1982
REJ09B0256-0200
Bit
15
14
13, 12
11 to 9
8
Bit Name
CKSL

CKDV[1:0] 00

REQEN
Initial
Value
0
0
All 0
0
R/W
R/W
R
R/W
R
R/W
Description
Operating Clock
Selects the source clock for the stream data transfer
clock
0: Peripheral clock 0 is used as the stream data
1: External input clock is used as the stream data
Reserved
This bit is always read as 0. The write value should
always be 0.
Operating Clock Division Ratio
These bits specify the division ratio when peripheral
clock 0 is selected as the stream data transfer clock.
00: Stream data transfer clock is 1/2 of peripheral
01: Stream data transfer clock is 1/4 of peripheral
10: Stream data transfer clock is 1/8 of peripheral
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
ST_REQ Pin Enable
Selects whether or not to use the ST_REQ pin.
0: ST_REQ pin is not used
1: ST_REQ pin is used
(1) At reception: ST_REQ is output when the free
(2) At transmission: Transmission is stopped when
transfer clock (stream data transfer clock is output
from the ST_CLK pin)
transfer clock (stream data transfer clock is input
from the ST_CLK pin)
space in FIFO is 8 bytes or less
ST_REQ is input
clock 0
clock 0
clock 0