R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 962

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.55 CAM Entry Table 0L to 31L Registers (TSU_ADRL0 to TSU_ADRL31)
TSU_ADRL0 to TSU_ADRL31 are entry tables referred to by the CAM in reception and relay.
Each of these registers sets the lower 16 bits of the 48-bit MAC address. Maximum 32 entries of
MAC addresses can be registered.
Note:
Rev. 2.00 May 22, 2009 Page 892 of 1982
REJ09B0256-0200
Bit
31 to 16
15 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Set the CAM entry tables following the procedure below.
1. Check that the ADSBSY bit in TSU_ADSBSY is cleared to 0.
2. Set the upper 32 bits of the MAC addresses by TSU_ADRH0 to TSU_ADRH31.
3. Set the lower 16 bits of the MAC addresses by TSU_ADRL0 to TSU_ADRL31.
Bit Name

ADRLn[15:0]
(n: 0 to 31)
R/W
31
15

R
0
0
R/W
30
14

R
0
0
R/W
29
13

R
0
0
Initial
Value
All 0
All 0
R/W
28
12

R
0
0
R/W
27
11

R
0
0
R/W Description
R
R/W MAC Address Bits
R/W
26
10

R
0
0
Reserved
These bits are always read as 0. The write value should
always be 0.
These bits set the lower 16 bits of the MAC address.
When the MAC address is 01-23-45-67-89-AB
(displayed in hexadecimal), set H'000089AB in this
register.
R/W
25

R
0
9
0
ADRLn[15:0] (n = 0 to 31)
R/W
24

R
0
8
0
R/W
23

R
0
7
0
R/W
22

R
0
6
0
R/W
21

R
0
5
0
R/W
20

R
0
4
0
R/W
19

R
0
3
0
R/W
18

R
0
2
0
17

R
0
1
0
R/W
16

R
0
0
0