R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 14

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.6
7.7
7.8
Section 8 L Memory.......................................................................................... 217
8.1
8.2
8.3
8.4
8.5
8.6
Section 9 Interrupt Controller (INTC)............................................................... 233
9.1
9.2
9.3
Rev. 2.00 May 22, 2009 Page xii of lxviii
Memory-Mapped Cache Configuration ............................................................................. 206
7.6.1
7.6.2
7.6.3
7.6.4
Store Queues ...................................................................................................................... 212
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
Notes on Using 32-Bit Address Extended Mode ............................................................... 215
Features.............................................................................................................................. 217
Register Descriptions......................................................................................................... 218
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
Operation ........................................................................................................................... 229
8.3.1
8.3.2
8.3.3
L Memory Protective Functions ........................................................................................ 231
Usage Notes ....................................................................................................................... 232
8.5.1
8.5.2
8.5.3
Note on Using 32-Bit Address Extended Mode................................................................. 232
Features.............................................................................................................................. 233
9.1.1
9.1.2
Input/Output Pins............................................................................................................... 240
Register Descriptions......................................................................................................... 241
9.3.1
9.3.2
IC Address Array.................................................................................................. 206
IC Data Array ....................................................................................................... 208
OC Address Array ................................................................................................ 209
OC Data Array...................................................................................................... 210
SQ Configuration.................................................................................................. 212
Writing to SQ........................................................................................................ 212
Transfer to External Memory ............................................................................... 213
Determination of SQ Access Exception................................................................ 214
Reading from SQ .................................................................................................. 214
On-Chip Memory Control Register (RAMCR) .................................................... 220
L Memory Transfer Source Address Register 0 (LSA0) ...................................... 221
L Memory Transfer Source Address Register 1 (LSA1) ...................................... 223
L Memory Transfer Destination Address Register 0 (LDA0) .............................. 225
L Memory Transfer Destination Address Register 1 (LDA1) .............................. 227
Access from the CPU and FPU............................................................................. 229
Access from the SuperHyway Bus Master Module .............................................. 229
Block Transfer ...................................................................................................... 229
Page Conflict ........................................................................................................ 232
L Memory Coherency........................................................................................... 232
Sleep Mode ........................................................................................................... 232
Interrupt Method................................................................................................... 235
Interrupt Types in INTC ....................................................................................... 236
Interrupt Control Register 0 (ICR0)...................................................................... 246
Interrupt Control Register 1 (ICR1)...................................................................... 248