R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 657

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
9, 8
7 to 3
2
Bit Name
PR[1:0]
—
AE
Initial
Value
00
0
All 0
R/W
R/W
R
R/(W)* Address Error Flag
Descriptions
Priority Mode 1, 0
Select the priority level between channels when there
are transfer requests for multiple channels
simultaneously.
00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
10: Setting prohibited
11: Round-robin mode
Reserved
These bits are always read as 0. The write value should
always be 0.
Indicates that an address error occurred during DMA
transfer.
This bit is set under following conditions:
•
•
•
bit in CHCR and the DME bit in DMAOR are set to 1.
0: No DMAC address error
[Clearing condition]
Writing 0 after AE = 1 is read.
However, when the AE bit is not cleared, always write 1
1: DMAC address error occurs
to this bit.
If this bit is set, DMA transfer is disabled even if the DE
The value set in SAR or DAR does not match to the
transfer size boundary.
The transfer source or transfer destination is invalid
space.
The transfer source or transfer destination is in
module stop mode
Section 14 Direct Memory Access Controller (DMAC)
Rev. 2.00 May 22, 2009 Page 587 of 1982
REJ09B0256-0200