R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1900

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 43 Electrical Characteristics
43.2.3
To use RTC power supply backup mode, the RTC clock should be supplied.
First bring the XRTCSTBI pin low, and then make sure that the STATUS0 and STATUS1 pins
have been pulled high and low, respectively. After that, turn off the power supplies (VCCQ,
AVCC), (VCCQ-DDR), and (VDD, VDD-PLL1 to 3, VDD-DLL1 to 3). The power supply VDD-
RTC should remain on, and the XRTCSTBI pin should remain low.
Turn on the power supplies (VCCQ, AVCC), (VCCQ-DDR), and (VDD, VDD-PLL1 to 3, VDD-
DLL1 to 3) while the XRTCSTBI pin is low. Only after the power-on oscillation settling time
(refer to section 43.4.1, Clock and Control Signal Timing) has elapsed after the power supplies
above become stable, bring the XRTCSTBI pin high and negate the PRESET pin to high level.
43.2.4
To use DDR-SDRAM power-supply backup mode, the DDR-SDRAM should be placed in the
self-refresh state. After the DDR-SDRAM is placed in the self-refresh state, bring the M-CKE pin
low. Make sure that the SELFS bit in the MIM register is set to 1, and then bring the M_BKPRST
pin low. After that, turn off the power supplies (VCCQ, AVCC, VDD-RTC) and (VDD, VDD-
PLL1 to 3, VDD-DLL1 to 3). The power supply VCCQ-DDR should remain on and the
M_BKPRST pin should remain low.
Turn on the power supplies (VCCQ, AVCC, VDD-RTC) and (VDD, VDD-PLL1 to 3, VDD-
DLL1 to 3) while the M_BKPRST pin is low. Only after the power-on oscillation settling time
(refer to section 43.4.1, Clock and Control Signal Timing) has elapsed after the power supplies
above become stable, negate the M_BKPRST and PRESET pins to high level.
43.2.5
When the power supply VCCQ-DDR is turned on at power-on, after being turned off, it is
recommended that the M_BKPRST pin is driven low to keep the M_CKE signal output low,
similarly to the DDR-SDRAM power supply backup sequence (refer to figure 18.1, DDR-
SDRAM Interface Operation when Turning System Power Supply On/Off).
The reason is to avoid the collision of the data buses of this LSI and the DDR-SDRAM each other,
keeping the CKE input of the DDR-SDRAM low at power-on.
Rev. 2.00 May 22, 2009 Page 1830 of 1982
REJ09B0256-0200
Standby)
Power-Off and Power-On Order in RTC Power-Supply Backup Mode (Hardware
Power-Off and Power-On Order in DDR-SDRAM Power-Supply Backup Mode
Note when DDR-SDRAM Power-Supply is Turned On