R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 623

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(1)
Figures13.17 is an example of a single-write cycle in host bus bridge mode. Figure 13.18 is an
example of a single read cycle in host bus bridge mode. Figure 13.19 is an example of a burst
write cycle in normal mode. And Figure 13.20 is an example of a burst read cycle in normal mode.
Note that the response speed of DEVSEL and TRDY differs according to the connected target
device. In host bus bridge mode, master accesses always use single read/write cycles. The issuing
of configuration transfers is only possible in host bus bridge mode.
Master Read/Write Cycle Timing
Figure 13.17 Master Write Cycle in Host Bus Bridge Mode (Single)
[Legend]
Addr:
AP:
Com:
PCICLK
AD[31:0]
PAR
CBE[3:0]
(C/BE[3:0])
PCIFRAME
IRDY
DEVSEL
TRDY
LOCK
IDSEL
REQ
GNT
PCI space address
Address parity
Command
Dn:
DPn:
BEn:
Addr
Com
nth data
nth data parity
nth data byte enable
BE0
AP
D0
Rev. 2.00 May 22, 2009 Page 553 of 1982
DP0
Section 13 PCI Controller (PCIC)
REJ09B0256-0200