R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 224

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Memory Management Unit (MMU)
Initial value:
Initial value:
Rev. 2.00 May 22, 2009 Page 154 of 1982
REJ09B0256-0200
Bit
31 to 5
4
3
2
1
R/W:
R/W:
Bit:
Bit:
Bit Name

R2
R1
LT
MT
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
Initial
Value
All 0
0
0
0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R/W
R/W
R/W
R/W
26
10
R
R
0
0
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Re-Fetch Inhibit 2 after Register Change
When MMUCR, PASCR, CCR, PTEH, or RAMCR is
changed, this bit controls whether re-fetch is
performed for the next instruction.
0: Re-fetch is performed
1: Re-fetch is not performed
Re-Fetch Inhibit 1 after Register Change
When a register allocated in addresses H'FF200000 to
H'FF2FFFFF is changed, this bit controls whether re-
fetch is performed for the next instruction.
0: Re-fetch is performed
1: Re-fetch is not performed
Re-Fetch Inhibit after LDTLB Execution
This bit controls whether re-fetch is performed for the
next instruction after the LDTLB instruction has been
executed.
0: Re-fetch is performed
1: Re-fetch is not performed
Re-Fetch Inhibit after Writing Memory-Mapped TLB
This bit controls whether re-fetch is performed for the
next instruction after writing memory-mapped
ITLB/UTLB while the AT bit in MMUCR is set to 1.
0: Re-fetch is performed
1: Re-fetch is not performed
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
R/W
R2
20
R
0
4
0
R/W
R1
19
R
0
3
0
R/W
18
LT
R
0
2
0
R/W
MT
17
R
0
1
0
R/W
MC
16
R
0
0
0