R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 334

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Interrupt Controller (INTC)
9.3.12
USERIMASK is a 32-bit readable and writable with conditions register that sets the acceptable
interrupt level. When addresses in area 7 are accessed using the MMU address translation
function, USERIMASK can be accessed in user mode. Since only USERIMASK is allocated in
the 64-Kbyte page (other INTC registers are allocated to a different area), it can be set to be
accessed in user mode.
Interrupts whose priority levels are lower than the level set in the UIMASK bit are masked. If the
value of H'F is set to the UIMASK bit, all interrupts other than the NMI are masked.
Interrupts whose priority levels are higher than the level set in the UIMASK bit are accepted under
the following conditions:
• The corresponding interrupt mask bit in the interrupt mask register is cleared to 0 (the interrupt
• The priority level set in the IMASK bit in SR is lower than that of the interrupt.
Even if interrupts are accepted, the UIMASK value is not changed.
USERIMASK is initialized to H'0000 0000 (all interrupts are enabled) when returning from a
power-on reset or a manual reset.
Rev. 2.00 May 22, 2009 Page 264 of 1982
REJ09B0256-0200
Bit
16
15 to 0
is enabled).
User Interrupt Mask Level Register (USERIMASK)
Bit Name
NMIFL
—
Initial
Value
0
All 0
R/W
R/W
R
Description
NMI Interrupt Request Signal Detection
Indicates whether an NMI interrupt request signal has
been detected. This bit is automatically set to 1 when
the INTC detects an NMI interrupt request. Write 0 to
clear the bit. Writing 1 is ignored.
[When reading]
1: NMI is detected
0: NMI is not detected
[When writing]
0: The NMI flag is cleared
1: Writing 1 is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.