R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1274

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 29 Serial I/O with FIFO (SIOF)
29.3.7
SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. SIRCR
can be specified only when the FL bit in SIMDR is specified as 1xxx (x: don't care.).
Rev. 2.00 May 22, 2009 Page 1204 of 1982
REJ09B0256-0200
Initial value:
Initial value:
Bit
31 to 16 SIRC0[15:0]
15 to 0
R/W:
R/W:
BIt:
BIt:
Receive Control Data Register (SIRCR)
Bit Name
SIRC1[15:0]
R/W
R/W
31
15
R/W
R/W
30
14
R/W
R/W
29
13
Initial
Value
Undefined
Undefined
R/W
R/W
28
12
R/W
R/W
27
11
R/W
R/W
R/W
R/W
R/W
26
10
Control Channel 0 Receive Data
Control Channel 1 Receive Data
Description
Store data received from the SIOF_RXD pin as control
channel 0 receive data. The position of the control
channel 0 data in the transmit or receive frame is
specified by the CD0A bit in SICDAR.
Store data received from the SIOF_RXD pin as control
channel 1 receive data. The position of the control
channel 1 data in the transmit or receive frame is
specified by the CD1A bit in SICDAR.
R/W
R/W
25
9
These bits are valid only when the CD0E bit in
SICDAR is set to 1.
These bits are valid only when the CD1E bit in
SICDAR is set to 1.
SIRC0[15:0]
SIRC1[15:0]
R/W
R/W
24
8
R/W
R/W
23
7
R/W
R/W
22
6
R/W
R/W
21
5
R/W
R/W
20
4
R/W
R/W
19
3
R/W
R/W
18
2
R/W
R/W
17
1
R/W
R/W
16
0

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