R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 336

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Interrupt Controller (INTC)
UIMASK level are held disabled, and correct operation may not be performed (for example, the
OS cannot switch tasks).
An example of the usage procedure is shown below.
1. Classify interrupts to A and B as described below and set the A priority higher than the B
2. Make the MMU settings so that the address space including USERIMASK can only be
3. Branch to the device driver.
4. Set the UIMASK bit to mask B interrupts in the device driver that is operating in user mode.
5. Process interrupts with high priority in the device driver.
6. Clear the UIMASK bit to 0 to return from processing in the device driver.
9.3.13
INT2PRI0 to INT2PRI13 are 32-bit readable/writable registers that set priorities (levels 31 to 0) of
the on-chip peripheral module interrupts. INT2PRI0 to INT2PRI13 are initialized to H'0000 0000
by a reset.
INT2PRI0 to INT2PRI13 can set 30 priority levels (32 types of interrupt requests) to individual
interrupt sources with five bits (interrupt requests are masked at H'00 and H'01).
Initial value:
Initial value:
Rev. 2.00 May 22, 2009 Page 266 of 1982
REJ09B0256-0200
priority.
A. Interrupts to be accepted in the device driver (interrupts to be used by the operating system:
B. Interrupts to be disabled in the device driver
accessed by the device driver in which interrupts should be disabled.
R/W:
R/W:
Bit:
Bit:
a timer interrupt etc.)
On-chip module Interrupt Priority Registers (INT2PRI0 to INT2PRI13)
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
26
10
0
0
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0

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