R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 179
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.3
5.3.1
In exception handling, the contents of the program counter (PC), status register (SR), and R15 are
saved in the saved program counter (SPC), saved status register (SSR), and saved general
register15 (SGR), and the CPU starts execution of the appropriate exception handling routine
according to the vector address. An exception handling routine is a program written by the user to
handle a specific exception. The exception handling routine is terminated and control returned to
the original program by executing a return-from-exception instruction (RTE). This instruction
restores the PC and SR contents and returns control to the normal processing routine at the point at
which the exception occurred. The SGR contents are not written back to R15 with an RTE
instruction.
The basic processing flow is as follows. For the meaning of the SR bits, see section 2,
Programming Model.
1. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR, respectively.
2. The block bit (BL) in SR is set to 1.
3. The mode bit (MD) in SR is set to 1.
4. The register bank bit (RB) in SR is set to 1.
5. In a reset, the FPU disable bit (FD) in SR is cleared to 0.
6. The exception code is written to bits 11 to 0 of the exception event register (EXPEVT) or
7. The CPU branches to the determined exception handling vector address, and the exception
5.3.2
The reset vector address is fixed at H'A0000000. Exception and interrupt vector addresses are
determined by adding the offset for the specific event to the vector base address, which is set by
software in the vector base register (VBR). In the case of the TLB miss exception, for example,
the offset is H'00000400, so if H'9C080000 is set in VBR, the exception handling vector address
will be H'9C080400. If a further exception occurs at the exception handling vector address, a
duplicate exception will result, and recovery will be difficult; therefore, addresses that are not to
be converted (in P1 and P2 areas) should be specified for vector addresses.
interrupt event register (INTEVT).
handling routine begins.
Exception Handling Functions
Exception Handling Flow
Exception Handling Vector Addresses
Rev. 2.00 May 22, 2009 Page 109 of 1982
Section 5 Exception Handling
REJ09B0256-0200
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