R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1840

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 41 User Break Controller (UBC)
Rev. 2.00 May 22, 2009 Page 1770 of 1982
REJ09B0256-0200
Bit
7, 6
5, 4
3
2, 1
Bit Name
CD
ID
—
RW
Initial
Value
All 0
All 0
0
All 0
R/W
R/W
R/W
R
R/W
Description
Bus Select
Specifies the bus to be included in the match
conditions. This bit is valid only when the operand
access cycle is specified as a match condition.
00:
Others: Reserved (setting prohibited)
Instruction Fetch/Operand Access Select
Specifies the instruction fetch cycle or operand access
cycle as the match condition.
00: Instruction fetch cycle or operand access cycle
01: Instruction fetch cycle
10: Operand access cycle
11: Instruction fetch cycle or operand access cycle
Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
Bus Command Select
Specifies the read/write cycle as the match condition.
This bit is valid only when the operand access cycle is
specified as a match condition.
00: Read cycle or write cycle
01: Read cycle
10: Write cycle
11: Read cycle or write cycle
Operand bus for operand access