R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 32

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

34.5 Usage Note....................................................................................................................... 1458
Section 35 USB Host Controller (USBH) ....................................................... 1459
35.1 Features............................................................................................................................ 1459
35.2 Pin Description ................................................................................................................ 1461
35.3 Register Description ........................................................................................................ 1462
35.4 Functional Description..................................................................................................... 1493
35.5 Connection Example of an External Circuit .................................................................... 1495
35.6 Usage Notes ..................................................................................................................... 1495
Rev. 2.00 May 22, 2009 Page xxx of lxviii
34.4.5 Receive Operation .............................................................................................. 1454
34.4.6 Serial Clock Control ........................................................................................... 1457
34.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation .......... 1458
34.5.2 Restrictions for Operation in Slave Mode........................................................... 1458
35.3.1 HcRevision Register (USBHR) .......................................................................... 1464
35.3.2 HcControl Register (USBHC) ............................................................................ 1465
35.3.3 HcCommandStatus Register (USBHCS) ............................................................ 1467
35.3.4 HcInterruptStatus Register (USBHIS) ................................................................ 1468
35.3.5 HcInterruptEnable Register (USBHIE) .............................................................. 1470
35.3.6 HcInterruptDisable Register (USBHID)............................................................. 1471
35.3.7 HcHCCA Register (USBHHCCA) ..................................................................... 1473
35.3.8 HcPeriodCurrentED Register (USBHPCED) ..................................................... 1473
35.3.9 HcControlHeadED Register (USBHCHED) ...................................................... 1474
35.3.10 HcControlCurrentED Register (USBHCCED) ................................................... 1474
35.3.11 HcBulkHeadED Register (USBHBHED)........................................................... 1475
35.3.12 HcBulkCurrentED Register (USBHBCED) ....................................................... 1475
35.3.13 HcDoneHead Register (USBHDHED) ............................................................... 1476
35.3.14 HcFmInterval Register (USBHFI)...................................................................... 1477
35.3.15 HcFrameRemaining Register (USBHFR)........................................................... 1478
35.3.16 HcFmNumber Register (USBHFN).................................................................... 1479
35.3.17 HcPeriodicStart Register (USBHPS).................................................................. 1480
35.3.18 HcLSThreshold Register (USBHLST) (Not supporting LowSpeed mode) ........ 1481
35.3.19 HcRhDescriptorA Register (USBHRDA)
35.3.20 HcRhDescriptorB Register (USBHRDB)
35.3.21 HcRhStatus Register (USBHRS)........................................................................ 1486
35.3.22 HcRhPortStatus[2] Register (USBHRPS2) ........................................................ 1488
35.3.23 ConfigurationControl Register (USBHSC) ........................................................ 1491
35.4.1 General Functionality ......................................................................................... 1493
35.6.1 External memory that USBH accesses................................................................ 1495
(Only one port is supported by this LSI.)............................................................ 1482
(Only one port is supported by this LSI.)............................................................ 1484