R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 33

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 36 USB Function Controller (USBF) .................................................1497
36.1 Features............................................................................................................................ 1497
36.2 Input/Output Pins ............................................................................................................. 1499
36.3 Register Descriptions ....................................................................................................... 1500
35.6.2 Issuing USB Bus Reset ....................................................................................... 1495
36.3.1 Interrupt Flag Register 0 (IFR0) ......................................................................... 1506
36.3.2 Interrupt Flag Register 1 (IFR1) ......................................................................... 1509
36.3.3 Interrupt Flag Register 2 (IFR2) ......................................................................... 1511
36.3.4 Interrupt Flag Register 3 (IFR3) ......................................................................... 1513
36.3.5 Interrupt Flag Register 4 (IFR4) ......................................................................... 1516
36.3.6 Interrupt Select Register 0 (ISR0)....................................................................... 1517
36.3.7 Interrupt Select Register 1 (ISR1)....................................................................... 1518
36.3.8 Interrupt Select Register 2 (ISR2)....................................................................... 1519
36.3.9 Interrupt Select Register 3 (ISR3)....................................................................... 1520
36.3.10 Interrupt Select Register 4 (ISR4)....................................................................... 1521
36.3.11 Interrupt Enable Register 0 (IER0) ..................................................................... 1522
36.3.12 Interrupt Enable Register 1 (IER1) ..................................................................... 1523
36.3.13 Interrupt Enable Register 2 (IER2) ..................................................................... 1524
36.3.14 Interrupt Enable Register 3 (IER3) ..................................................................... 1525
36.3.15 Interrupt Enable Register 4 (IER4) ..................................................................... 1526
36.3.16 EP0i Data Register (EPDR0i)............................................................................. 1527
36.3.17 EP0o Data Register (EPDR0o) ........................................................................... 1528
36.3.18 EP0s Data Register (EPDR0s) ............................................................................ 1529
36.3.19 EP1 Data Register (EPDR1) ............................................................................... 1530
36.3.20 EP2 Data Register (EPDR2) ............................................................................... 1531
36.3.21 EP3 Data Register (EPDR3) ............................................................................... 1532
36.3.22 EP4 Data Register (EPDR4) ............................................................................... 1533
36.3.23 EP5 Data Register (EPDR5) ............................................................................... 1534
36.3.24 EP0o Receive Data Size Register (EPSZ0o) ...................................................... 1535
36.3.25 EP1 Receive Data Size Register (EPSZ1) .......................................................... 1536
36.3.26 EP4 Receive Data Size Register (EPSZ4) .......................................................... 1537
36.3.27 Trigger Register (TRG)....................................................................................... 1538
36.3.28 Data Status Register (DASTS)............................................................................ 1539
36.3.29 FIFO Clear Register 0 (FCLR0) ......................................................................... 1540
36.3.30 FIFO Clear Register 1 (FCLR1) ......................................................................... 1541
36.3.31 DMA Transfer Setting Register (DMA) ............................................................. 1542
36.3.32 Endpoint Stall Register 0 (EPSTL0)................................................................... 1543
36.3.33 Endpoint Stall Register 1 (EPSTL1)................................................................... 1544
36.3.34 Configuration Value Register (CVR) ................................................................. 1545
Rev. 2.00 May 22, 2009 Page xxxi of lxviii