R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 826

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 21 Compare Match Timer (CMT)
Note:
21.2.3
CMCNT is a 32-bit register that is used as an up-counter.
A counter operation is set by the compare match timer control/status register (CMCSR).
Therefore, set CMCSR first, before starting a channel operation corresponding to the compare
match timer start register (CMSTR). When the 16-bit counter operation is selected by the CMS
bit, bits 15 to 0 of this register become valid. When the register should be written to, write the data
that is added H'0000 to the upper half in a 32-bit operation. The contents of this register are
initialized to H'00000000.
21.2.4
CMCOR is a 32-bit register that sets the compare match period with CMCNT for each channel.
When the 16-bit counter operation is selected by the CMS bit in CMCSR, bits 15 to 0 of this
register become valid. When the register should be written to, write the data that is added H'0000
to the upper half in a 32-bit operation.
An overflow is detected when CMCNT is cleared to 0 and this register is H'FFFFFFFF. The
contents of this register are initialized to H'FFFFFFFF.
Rev. 2.00 May 22, 2009 Page 756 of 1982
REJ09B0256-0200
Bit
2 to 0
*
Compare Match Timer Counter (CMCNT)
Compare Match Timer Constant Register (CMCOR)
Bit Name
CKS[2:0] All 0
Only 0 can be written to clear the flag.
Initial
Value
R/W
R/W
Description
Clock Select
These bits select the clock input to CMCNT. When the
STRn (n: 4 to 0) bit in CMSTR is set to 1, CMCNT begins
incrementing with the clock selected by these bits.
000: Pck0/8
001: Pck0/32
010: Pck0/128
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited