R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 494

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 DDR-SDRAM Interface (DDRIF)
Rev. 2.00 May 22, 2009 Page 424 of 1982
REJ09B0256-0200
Bit
63 to 3
2 to 0
Bit Name

SMS
Initial
Value
All 0
000
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SDRAM Mode Select
These bits initialize the DDR-SDRAM at a power-on or
after release of a reset. If this bit is set by software, the
following commands are issued. For details on the
initialization procedure, see section 12.5.2, DDR-
SDRAM Initialization Sequence. After the DDR-
SDRAM has been initialized, normal operation (000) is
specified.
000: Normal operation
001: The NOP command is issued (valid only when the
010: The PREALL command is issued (valid only when
011: The M_CKE pin is enabled. At that time, the
100: The REFA (auto) refresh command is issued
Settings other than above are prohibited. If such
settings are made, correct operation is not guaranteed.
Note that setting the M_CKE pin low by the PCKE bit in
MIM is used to reduce the DDR-SDRAM power
consumption.
DCE bit in MIM is set to 1).
the DCE bit in MIM is set to 1).
DESELECT command is issued (valid only when
the DCE bit in MIM is set to 1).
(valid only when the DCE bit in MIM is set to 1).