R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 567

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
7
6
5
Bit Name
APEDI
SEDI
DPEITW
Initial
Value
0
0
0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
Address Parity Error Detection Interrupt
Indicates an address parity error has been detected.
When both the PER and SERRE bits in the PCI
command register are set to 1, an address parity
error is detected.
0: Address parity error detection interrupt does not
[Clear condition]
Write 1 to this bit (write clear).
1: Address parity error detection interrupt occurs
[Set condition]
When an address parity error detection interrupt
occurs.
SERR Detection Interrupt
Indicates that the assertion of the SERR signal has
been detected when the PCIC operates in host bus
bridge mode.
0: SERR detection interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: SERR detection interrupt occurs
[Set condition]
When a SERR detection interrupt occurs.
Data Parity Error Interrupt for Target Write
Indicates that a data parity error has been detected
during a target write access (only detected when
PCICMD.PER is set to 1) when the PCIC functions
as a target.
0: Data parity error detection interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Data parity error detection interrupt occurs
[Set condition]
When a data parity error detection interrupt occurs.
occur
Rev. 2.00 May 22, 2009 Page 497 of 1982
Section 13 PCI Controller (PCIC)
REJ09B0256-0200