R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1406

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 31 Multimedia Card Interface (MMCIF)
• Write 1 to the CMDOFF bit when a CRC error (CRCERI) or command timeout error (CTERI)
• Clear the FIFO by writing 1 to the CMDOFF bit when a CRC error (CRCERI) or data timeout
Note: In multiblock transfer, when the command sequence is ended (write 1 to the CMDOFF
Rev. 2.00 May 22, 2009 Page 1336 of 1982
REJ09B0256-0200
Input/output pins
occurs in the command response reception.
error (DTERI) occurs in the read data reception.
(FIFO_FULL)
(RD_CONTI)
(CMDOFF)
CMDSTRT
INTSTR0
(START)
(CWRE)
(BUSY)
(CMDI)
(CRPI)
OPCR
CSTR
(REQ)
CMD
(DTI)
(FFI)
CLK
DAT
bit) before command response reception (CRPI), the command response may not be
received correctly. Therefore, to receive the command response, the command sequence
must be continued (set the RD_CONTI bit to 1) until the command response reception
ends.
Figure 31.7 Example of Command Sequence for Commands with Read Data
CMD17 (READ_SINGLE_BLOCK)
Command
transmission
started
Command
(Block Size ≤ FIFO Size)
Single block read command execution sequence
Command response
Read data