R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 537

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
13
12
11
10, 9
8
Bit Name
RMA
RTA
STA
DEVSEL
MDPE
Initial
Value
0
0
0
01
0
R/W
SH: R/WC
PCI: R/WC
SH: R/WC
PCI: R/WC
SH: R/WC
PCI: R/WC
SH: R
PCI: R
SH: R/WC
PCI: R/WC
Description
Master Abort Receive Status
Indicates that the PCIC has terminated a transaction
with a master abort when the PCIC is a master.
0: PCIC has not terminated a transaction with a
1: PCIC has terminated a transaction with a master
Target Abort Receive Status
Indicates that a transaction is terminated by a target
device with a target abort when the PCIC functions as
a master.
0: Transaction has not been terminated with a target
1: Transaction has been terminated with a target abort
Target Abort Execution Status
Indicates that the PCIC has terminated a transaction
with a target-abort when the PCIC functions as a
target.
0: PCIC has not terminated a transaction with a
1: PCIC has terminated a transaction with target-abort
DEVSEL Timing Status
Indicate the response timing status of the DEVSEL
signal when the PCIC functions as a target.
00: Fast (not support)
01: Medium
10: Slow (not support)
11: Reserved
Data parity error
Indicates that the PCIC has asserted the PERR signal
or detected the assertion of the PERR signal if the
PCIC functions as a master. Only when the parity
response bit has been set to 1, this bit is set to 1.
0: Data parity error has not been generated
1: Data parity error has been generated
master abort
abort
abort
target-abort
Rev. 2.00 May 22, 2009 Page 467 of 1982
Section 13 PCI Controller (PCIC)
REJ09B0256-0200