R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 27

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 27 Serial Communication Interface with FIFO (SCIF) ......................1061
27.1 Features............................................................................................................................ 1061
27.2 Input/Output Pins ............................................................................................................. 1067
27.3 Register Descriptions ....................................................................................................... 1068
27.4 Operation ......................................................................................................................... 1094
27.5 SCIF Interrupt Sources and the DMAC ........................................................................... 1115
27.6 Usage Notes ..................................................................................................................... 1117
Section 28 Serial Communication Interface with FIFO/IrDA Interface
28.1 Features............................................................................................................................ 1121
28.2 Input/Output Pins ............................................................................................................. 1125
28.3 Register Descriptions ....................................................................................................... 1126
26.5.2 Master Receiver .................................................................................................. 1057
26.5.3 Master Transmitter—Restart—Master Receiver ................................................ 1058
27.3.1 Receive Shift Register (SCRSR)......................................................................... 1070
27.3.2 Receive FIFO Data Register (SCFRDR) ............................................................ 1070
27.3.3 Transmit Shift Register (SCTSR) ....................................................................... 1071
27.3.4 Transmit FIFO Data Register (SCFTDR) ........................................................... 1071
27.3.5 Serial Mode Register (SCSMR).......................................................................... 1072
27.3.6 Serial Control Register (SCSCR)........................................................................ 1075
27.3.7 Serial Status Register (SCFSR) .......................................................................... 1079
27.3.8 Bit Rate Register (SCBRR) ................................................................................ 1085
27.3.9 FIFO Control Register (SCFCR) ........................................................................ 1086
27.3.10 Transmit FIFO Data Count Register (SCTFDR) ................................................ 1088
27.3.11 Receive FIFO Data Count Register (SCRFDR).................................................. 1088
27.3.12 Serial Port Register (SCSPTR) ........................................................................... 1089
27.3.13 Line Status Register (SCLSR) ............................................................................ 1092
27.3.14 Serial Error Register (SCRER) ........................................................................... 1093
27.4.1 Overview............................................................................................................. 1094
27.4.2 Operation in Asynchronous Mode ...................................................................... 1096
27.4.3 Operation in Clocked Synchronous Mode .......................................................... 1106
28.3.1 Receive Shift Register (SCRSR)......................................................................... 1128
28.3.2 Receive FIFO Data Register (SCFRDR) ............................................................ 1128
28.3.3 Transmit Shift Register (SCTSR) ....................................................................... 1129
28.3.4 Transmit FIFO Data Register (SCFTDR) ........................................................... 1129
28.3.5 Serial Mode Register (SCSMR).......................................................................... 1130
28.3.6 Serial Control Register (SCSCR)........................................................................ 1133
28.3.7 Serial Status Register (SCFSR) .......................................................................... 1137
(SCIF/IrDA)...................................................................................1121
Rev. 2.00 May 22, 2009 Page xxv of lxviii