R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 62

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Caches
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Section 8 L Memory
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Section 9 Interrupt Controller (INTC)
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Table 9.8
Table 9.9
Section 10 SuperHyway Bus Bridge (SBR)
Table 10.1
Table 10.2
Section 11 Local Bus State Controller (LBSC)
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 11.7
Table 11.8
Table 11.9
Table 11.10
Table 11.11
Table 11.12
Table 11.13
Table 11.14
Rev. 2.00 May 22, 2009 Page lx of lxviii
Cache Features...................................................................................................... 187
Store Queue Features ............................................................................................ 187
Register Configuration.......................................................................................... 190
Register States in Each Processing State .............................................................. 190
L Memory Addresses............................................................................................ 217
Register Configuration.......................................................................................... 218
Register Status in Each Processing State .............................................................. 219
Protective Function Exceptions to Access L Memory.......................................... 231
Interrupt Types...................................................................................................... 236
INTC Pin Configuration ....................................................................................... 240
INTC Register Configuration ............................................................................... 241
Register States in Each Operating Mode .............................................................. 244
Interrupt Request Sources and INT2PRI0 to INT2PRI13..................................... 267
RL[3:0], IRL[7:4] Pins and Interrupt Levels ........................................................ 294
Interrupt Exception Handling and Priority............................................................ 297
Interrupt Response Time....................................................................................... 308
Switching Sequence of IRQ7/IRL7 to IRQ0/IRL0 Pin Function ......................... 310
Register Configuration.......................................................................................... 314
Register State in Each Operating Mode................................................................ 314
Pin Configuration.................................................................................................. 322
LBSC External Memory Space Map .................................................................... 325
Setting of bus width for area 0.............................................................................. 328
Correspondence between External Pin (MD5) and Endian .................................. 329
PCMCIA Interface Features ................................................................................. 329
PCMCIA Support Interface .................................................................................. 330
Register Configuration.......................................................................................... 333
Register State in Each Operating Made. ............................................................... 333
32-Bit External Device/Big-Endian Access and Data Alignment......................... 358
16-Bit External Device/Big-Endian Access and Data Alignment..................... 358
8-Bit External Device/Big-Endian Access and Data Alignment ...................... 359
32-Bit External Device/Little-Endian Access and Data Alignment.................. 360
16-Bit External Device/Little-Endian Access and Data Alignment.................. 360
8-Bit External Device/Little-Endian Access and Data Alignment.................... 361