R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 507

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.5.7
The DDRIF is supported only when the clock ratio between the SuperHyway bus clock and the
external memory clock is 1:1 (DDR266 or DDR200). The maximum operating frequency for the
SuperHyway bus is 133 MHz. The minimum operating frequency depends on the DDR-SDRAM
clock frequency. Therefore see the DDR-SDRAM datasheet.
12.5.8
The clock supplied to the DDRIF is stopped in the following three modes:
• DDR-SDRAM power supply backup mode
• Software standby mode
• RTC power supply backup mode
Since the clock is not supplied in the above cases, auto-refreshing is not performed. As a result,
the refresh cycle is not held and then the DDR-SDRAM data will be damaged. To prevent this, the
DDR-SDRAM should enter the self-refresh state through software before the clock supply is
stopped. For details on entering/canceling the self-refresh mode, see section 12.5.5 (1), Self-
Refresh Mode.
12.5.9
This memory controller automatically opens the DDR-SDRAM bank by memory access
(read/write). When issuing the REFA command with the SMS bits in SCR, be sure to close the
bank by issuing the PREALL command with the SMS bits in SCR. This operation is also
necessary when SCR is used to perform concentrated refresh (REFA) on all rows in the memory
before self-refresh operations.
12.5.10 Note on Timing of Connected DDR-SDRAM
This memory controller only supports memory in which the number of cycles (tRAP) required
from issuing an ACT command to issuing a read or write with auto-precharge command and the
number of cycles (tRCD) required from issuing an ACT command to issuing a read or write
command are the same. If the two numbers differ, the DDR-SDRAM should be accessed in bank-
open mode.
Operating Frequency
Note on Clock Stop
Using SCR to Issue REFA Commands (Outside the Initialization Sequence)
Section 12 DDR-SDRAM Interface (DDRIF)
Rev. 2.00 May 22, 2009 Page 437 of 1982
REJ09B0256-0200