R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 484

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 DDR-SDRAM Interface (DDRIF)
12.3
12.3.1
Data Alignment in DDR-SDRAM: The DDRIF supports both big endian mode where an address
of the upper byte is 0 and little endian mode where an address of the lower byte is 0. These modes
can be switched by using external pins at a power-on reset.
The data alignment shown in the following tables is used when access is made from the peripheral
modules. The data alignment in little endian mode differs from that in the physical memory map
of the DDR-SDRAM.
Table 12.2 Access and Data Alignment in Little Endian Mode (External Bus Width is 32
Rev. 2.00 May 22, 2009 Page 414 of 1982
REJ09B0256-0200
Byte access at address 0
Byte access at address 1
Byte access at address 2
Byte access at address 3
Byte access at address 4
Byte access at address 5
Byte access at address 6
Byte access at address 7
Word access at address 0
Word access at address 2
Word access at address 4
Word access at address 6
Longword access at address 0 Data 31 to 24
Longword access at address 4 Data 31 to 24
Quadword access at address 0
(first time: address 0)
Quadword access at address 0
(second time: address 4)
Data Conversion
Data Alignment
Bits)
M_D31 to M_D24 M_D23 to M_D16 M_D15 to M_D8
Data 7 to 0
Data 7 to 0
Data 15 to 8
Data 15 to 8
Data 31 to 24
Data 63 to 56
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 23 to 16
Data 23 to 16
Data 23 to 16
Data 55 to 48
Data 7 to 0
Data 7 to 0
Data 15 to 8
Data 15 to 8
Data 15 to 8
Data 15 to 8
Data 15 to 8
Data 47 to 40
M_D7 to M_D0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 39 to 32

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