R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1132

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 27 Serial Communication Interface with FIFO (SCIF)
• Full-duplex communication capability
• On-chip baud rate generator allows any bit rate to be selected.
• Choice of serial clock source: internal clock from baud rate generator or external clock from
• Four interrupt sources
• The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA
• When not in use, the SCIF can be stopped by halting its clock supply to reduce power
• In asynchronous mode, modem control functions (SCIF0_RTS, SCIF1_RTS, SCIF0_CTS, and
• The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
• In asynchronous mode, a timeout error (DR) can be detected during reception.
Figure 27.1 shows a block diagram of the SCIF. Figures 27.2 to 27.6 show block diagrams of the
I/O ports in SCIF. There are two channels in this LSI. In figures 27.1 to 27.6, the channels are
omitted and explained.
Rev. 2.00 May 22, 2009 Page 1062 of 1982
REJ09B0256-0200
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling continuous
serial data transmission and reception.
SCIF_SCK0 or SCIF_SCK1 pin
There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive-error—that can issue requests independently.
transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
consumption.
SCIF1_CTS) are provided.
the receive data in the receive FIFO register, can be ascertained.