R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 669

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 14.3 shows how the priority changes when channel 0 and channel 3 transfers are requested
simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC
operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
4. When the channel 0 transfer ends, channel 0 becomes lowest priority.
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
6. When the channel 1 transfer ends, channel 1 becomes lowest priority.
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel
transfer).
waiting)
(channel 3 waits for transfer).
3 becomes the lowest priority.
Transfer request Waiting channel(s) DMAC operation
(1) Channels 0 and 3
Figure 14.3 Changes in Channel Priority in Round-Robin Mode
(3) Channel 1
1,3
3
3
None
(2) Channel 0 transfer
(4) Channel 0 transfer
(5) Channel 1 transfer
(6) Channel 1 transfer
(7) Channel 3 transfer
(8) Channel 3 transfer
start
ends
starts
ends
starts
ends
Section 14 Direct Memory Access Controller (DMAC)
Priority order
changes
Priority order
changes
Priority order
changes
Rev. 2.00 May 22, 2009 Page 599 of 1982
Channel priority
0 > 1 > 2 > 3 > 4 > 5
1 > 2 > 3 > 4 > 5 > 0
2 > 3 > 4 > 5 > 0 > 1
4 > 5 > 0 > 1 > 2 > 3
REJ09B0256-0200