R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1468

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 33 Audio Codec Interface (HAC)
33.3.2
HACCSAR is a 32-bit read/write register that specifies the address of the codec register to be read
/written. When requesting a write to/read from a codec register, write the command register
address to HACCSAR. Then the HAC transmits this register address to the codec via slot 1.
After the codec has responded to a read request (HACRSR.STARY = 1), the status address
received via slot 1 can be read out from HACCSAR.
Rev. 2.00 May 22, 2009 Page 1398 of 1982
REJ09B0256-0200
Initial value:
Initial value:
Bit
31 to 20
19
R/W:
R/W:
Bit:
Bit:
Command/Status Address Register (HACCSAR)
Bit Name

RW
R/W
31
−
15
R
0
0
R/W
CA/SA[3:0]
−
30
14
R
0
0
R/W
29
13
−
R
0
0
Initial
Value
All 0
0
R/W
−
28
12
R
0
0
−
27
11
R/W
R
R/W
R
R
0
0
26
10
−
R
R
0
0
Description
Reserved
Always 0 for read and write.
Codec Read/Write Command
0: Notifies the off-chip codec device of a write access to
1: Notifies the off-chip codec device of a read access to
25
−
R
R
0
9
0
the register specified in the address field (CA6/SA6
to CA0/SA0).
Write the data to HACCSDR in advance.
When HACACR.TX12_ATOMIC is 1, the HAC
transmits HACCSAR and HACCSDR as a pair in the
same Tx frame.
When HACACR.TX12_ATOMIC is 0, transmission of
HACCSAR and HACCSDR in the same Tx frame is
not guaranteed.
the register specified in the address field (CA6/SA6
to CA0/SA0).
24
−
R
R
0
8
0
SLREQ[3:12]
23
−
R
R
0
7
0
22
−
R
R
0
6
0
21
−
R
R
0
5
0
20
−
R
R
0
4
0
R/W
RW
19
R
0
3
0
R/W
18
R
0
2
0
CA/SA[6:4]
R/W
17
−
R
0
1
0
R/W
16
−
R
0
0
0