R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 335

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

To prevent incorrect writing, this register can only be written to with bits 31 to 24 set to H'A5.
Initial value:
Initial value:
Procedure for Using User Interrupt Mask Level Register
This function is used to save time by disabling interrupts whose priorities are low when a high
priority interrupt is processed in the device driver.
Setting the interrupt mask level in USERIMASK disables interrupts having an equal or lower
priority level than the specified mask level. This function can disable less-urgent interrupts in a
task (such as device driver) operating in user mode to accelerate urgent processing.
USERIMASK is allocated to a different 64-Kbyte page than where the other INTC registers are
allocated. When accessing this register in user mode, translate the address through the MMU. In
the system that uses a multitasking OS, processes that can access USERIMASK must be
controlled by using memory protection functions of the MMU. When terminating the task or
switching to another task, be sure to clear USERIMASK to 0 before quitting the task. If the
UIMASK bits are left set to a non-zero value, interrupts which are not higher in priority than the
Bit
31 to 24 —
23 to 8
7 to 4
3 to 0
R/W:
R/W:
Bit:
Bit:
Bit Name
—
—
UIMASK
R/W
31
−
15
−
R
0
0
R/W
30
14
−
−
R
0
0
R/W
Initial
Value
H'00
All 0
H'0
All 0
29
13
−
−
R
0
0
R/W
28
12
−
−
R
0
0
R/W
R/W
R
R/W
R
R/W
27
11
−
−
R
0
0
R/W
26
10
−
−
R
0
0
Description
To write a value to bits 7 to 4, write H'A5 to them.
These bits are always read as 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
Interrupt Mask Level
Masks interrupts whose priority levels are lower than
the level set in the UIMASK bit.
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
25
−
−
R
0
9
0
R/W
24
−
−
R
0
8
0
R/W
23
−
R
0
7
0
Rev. 2.00 May 22, 2009 Page 265 of 1982
R/W
22
R
UIMASK
−
0
6
0
Section 9 Interrupt Controller (INTC)
R/W
21
−
R
0
5
0
R/W
20
−
R
0
4
0
19
−
−
R
R
0
3
0
REJ09B0256-0200
18
−
−
R
R
0
2
0
17
−
−
R
R
0
1
0
16
−
−
R
R
0
0
0