R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 976

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.69 E-DMAC Mode Register (EDMR)
EDMR is a 32-bit readable/writable register that specifies E-DMAC resetting and the
transmit/receive descriptor length. This register is to be set before the transmitting or receiving
function is enabled (before the TR bit in EDTRR or the RR bit in EDRRR is set to 1). However,
the SWRR and SWRT bits can be written to even after the transmitting or receiving function is
enabled. If a software reset is executed with this register during data transmission, abnormal data
may be transmitted on the line. Execute a software reset with this register before specifying the
transmit/receive descriptor length or modifying the settings of TDLAR, RDLAR, and so forth, the
setting of ECMR (E-MAC mode register), and the settings of registers related to the E-DMAC and
E-MAC operation.
To execute a software reset with this register, 1 must be written to both the SWRT and SWRR bits
simultaneously. Writing 1 to the SWRT and SWRR bits initializes the E-MAC registers and E-
DMAC registers, except for TDLAR, RDLAR, and RMFCR of the E-DMAC. The TSU registers
(registers whose names are prefixed with TSU_) are not initialized. Writing 1 to the SWRT and
SWRR bits in EDMR0 initializes the registers related to the E-DMAC0 and E-MAC-0, whereas,
writing 1 to the SWRT and SWRR bits in EDMR1 initializes the registers related to the E-
DMAC1 and E-MAC-1. When relay operations are enabled in the TSU by specifying the relay
enable register (port 0 to 1) (TSU_FWEN0) and relay enable register (port 1 to 0) (TSU_FWEN1),
a software reset should not be performed using this register. Note that during the period a software
reset is issued (for 64 cycles of the internal bus clock Bck), accesses to all Ethernet-related
registers are prohibited.
Initial value:
Initial value:
Rev. 2.00 May 22, 2009 Page 906 of 1982
REJ09B0256-0200
R/W:
R/W:
Bit:
Bit:
31
15
−
−
R
R
0
0
30
14
−
−
R
0
R
0
29
−
13
−
R
R
0
0
28
−
12
−
R
R
0
0
27
11
−
−
R
R
0
0
26
10
−
−
R
R
0
0
25
−
−
R
R
0
9
0
24
−
−
R
R
0
8
0
23
−
−
R
R
0
7
0
R/W
DE
22
−
R
0
6
0
R/W
21
−
R
0
5
0
DL[1:0]
R/W
20
−
R
0
4
0
19
−
R
−
R
0
3
0
18
−
R
−
R
0
2
0
SWRT SWRR
R/W
17
−
R
0
1
0
R/W
16
−
R
0
0
0