R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 474
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 Local Bus State Controller (LBSC)
11.5.8
Wait Cycles between Accesses
A problem associated with higher operating frequencies for external memory buses is that the data
buffer turn-off after completion of a read from a low-speed device may be too slow, causing a
collision with the data in the next access, and resulting in lower reliability or malfunctions. To
prevent this problem, this module provides a data collision prevention function. It stores the
preceding access area and the type of read/write and inserts a wait cycle before the access cycle if
there is a possibility of a bus collision when the next access is started. The process for wait cycle
insertion consists of inserting idle cycles between the access cycles as shown in section 11.4.3,
CSn Bus Control Register (CSnBCR). If bits IWW, IWRWD, IWRWS, IWRRD and IWRRS in
CSnBCR (n = 0 to 2 and 4 to 6) are used to set the number of idle cycles between accesses, the
number of inserted idle cycles is only the specified number of idle cycles minus the number of idle
cycles specified by the bits.
When bus arbitration is performed, the bus is released after wait cycles are inserted between the
cycles.
When a DMA transfer (dual address mode) is performed, wait cycles are inserted as set in
CSnBCR idle cycle bits.
When access the MPX interface area continuously after read access, 1 wait cycle is inserted even
if set the wait cycle to 0.
When the access size is 8-byte or 16-byte, wait cycles are inserted every 4-byte access.
Rev. 2.00 May 22, 2009 Page 404 of 1982
REJ09B0256-0200
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