R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 39

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

43.4 AC Characteristics ........................................................................................................... 1835
43.5 A/D, D/A Converter Characteristics ................................................................................ 1902
43.6 AC Characteristic Test Conditions................................................................................... 1903
43.7 Change in Delay Time Based on Load Capacitance ........................................................ 1904
Appendix
A.
B.
C.
D.
E.
F.
G.
H.
I.
43.4.1 Clock and Control Signal Timing ....................................................................... 1836
43.4.2 Control Signal Timing ........................................................................................ 1840
43.4.3 Bus Timing ......................................................................................................... 1842
43.4.4 DDRIF Signal Timing ........................................................................................ 1860
43.4.5 INTC Module Signal Timing.............................................................................. 1863
43.4.6 External CPU Interface Read/Write Access Timing........................................... 1865
43.4.7 PCIC Module Signal Timing .............................................................................. 1867
43.4.8 DMAC Module Signal Timing ........................................................................... 1869
43.4.9 TMU Module Signal Timing .............................................................................. 1870
43.4.10 16-bit Timer Pulse Unit (TPU) Timing............................................................... 1871
43.4.11 GETHER Module Signal Timing ....................................................................... 1872
43.4.12 Stream Interface Module Timing........................................................................ 1878
43.4.13 I
43.4.14 SCIF Module Signal Timing............................................................................... 1884
43.4.15 SIOF Module Signal Timing .............................................................................. 1886
43.4.16 SIM Module Signal Timing ................................................................................ 1890
43.4.17 MMCIF Module Signal Timing.......................................................................... 1891
43.4.18 HAC Interface Module Signal Timing................................................................ 1893
43.4.19 SSI Interface Module Signal Timing .................................................................. 1895
43.4.20 USB Module Signal Timing ............................................................................... 1897
43.4.21 LCDC Module Signal Timing ............................................................................ 1898
43.4.22 GPIO Signal Timing ........................................................................................... 1899
43.4.23 H-UDI Module Signal Timing............................................................................ 1900
43.5.1 A/D Converter Characteristics ............................................................................ 1902
43.5.2 D/A Converter Characteristics ............................................................................ 1902
CPU Operation Mode Register (CPUOPM) .................................................................... 1905
Instruction Prefetching and Its Side Effects..................................................................... 1907
Speculative Execution for Subroutine Return.................................................................. 1908
List of Mode Control Pins and Schematic Diagram of External Circuits ........................ 1909
Notes on Board Design .................................................................................................... 1911
Package Dimensions ........................................................................................................ 1914
Pin States.......................................................................................................................... 1915
Handling of Unused Pins ................................................................................................. 1933
Version Registers ............................................................................................................. 1945
.......................................................................................................1905
2
C Bus Interface Timing .................................................................................... 1882
Rev. 2.00 May 22, 2009 Page xxxvii of lxviii