R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 651

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
19
18
Bit Name
HE
HIE
Initial
Value
0
0
R/W
R/(W)* Half End Flag
R/W
Descriptions
After HIE (bit 18) is set to 1 and the number of transfers
become half of TCR (1 bit shift to right) which is set
before transfer starts, HE becomes 1.
This bit is set to 1 when the TCR value is equal to (TCR
set before transfer)/2: TCR value is set to even number
of times (TCR set before transfer -1)/2: TCR value is
set to odd number of times 8,388,608 (H'0080 0000):
TCR value is set to the maximum number of times
(H'0000 0000)
The HE bit is not set when transfers are ended by an
NMI interrupt or address error, or by clearing the DE bit
or the DME bit in DMAOR before the number of
transfers is decreased to half of the TCR value set
preceding the transfer. The HE bit is kept set when the
transfer ends by an NMI interrupt or address error, or
clearing the DE bit (bit 0) or the DME bit in DMAOR
after the HE bit is set to 1. To clear the HE bit, write 0
after reading 1 in the HE bit. However, when the HE bit
is not cleared, always write 1 to this bit. This bit is valid
only in CHCR0 to CHCR3.
0: During the DMA transfer or DMA transfer has been
[Clearing condition]
Writing 0 after HE = 1 is read.
1: TCR = (TCR set before transfer)/2
Half End Interrupt Enable
Specifies whether an interrupt request is generated to
the CPU when the number of transfers is decreased to
half of the TCR value set preceding the transfer. When
the HIE bit is set to 1 and the HE bit is set, an interrupt
request is generated to the CPU. Clear this bit to 0
while reload mode is set. This bit is valid in CHCR0 to
CHCR3.
0: Half end Interrupt disabled
1: Half end Interrupt enabled
interrupted
TCR > (TCR set before transfer)/2
Section 14 Direct Memory Access Controller (DMAC)
Rev. 2.00 May 22, 2009 Page 581 of 1982
REJ09B0256-0200