R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 845

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
7
6 to 5
4
3
2 to 1
Bit Name
CF
—
CIE
AIE
—
0
Initial
Value
Undefined R/W
Undefined R
0
Undefined R
R/W
R/W
R/W
Description
Carry Flag
This flag is set to 1 on generation of a second counter
carry, or a 64 Hz counter carry when the 64 Hz counter
is read. The count register value read at this time is not
guaranteed, and so the count register must be read
again.
0: No second counter carry, or 64 Hz counter carry
[Clearing condition]
When 0 is written to CF
1: Second counter carry, or 64 Hz counter carry when
[Setting conditions]
Generation of a second counter carry, or a 64 Hz
counter carry when the 64 Hz counter is read
When 1 is written to CF
Reserved
The initial value of these bits is undefined. A write to
these bits is invalid, but the write value should always
be 0.
Carry Interrupt Enable Flag
Enables or disables interrupt generation when the carry
flag (CF) is set to 1.
0: Carry interrupt is not generated when CF flag is set
1: Carry interrupt is generated when CF flag is set to 1
Alarm Interrupt Enable Flag
Enables or disables interrupt generation when the
alarm flag (AF) is set to 1.
0: Alarm interrupt is not generated when AF flag is set
1: Alarm interrupt is generated when AF flag is set to 1
Reserved
The initial value of these bits is undefined. A write to
these bits is invalid, but the write value should always
be 0.
when 64 Hz counter is read
64 Hz counter is read
to 1
to 1
Rev. 2.00 May 22, 2009 Page 775 of 1982
Section 22 Realtime Clock (RTC)
REJ09B0256-0200