AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 110

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

16.6
16.6.1
110
Bulk/Interrupt Transactions
AT8xC51SND2C/MP3B
Bulk/Interrupt OUT Transactions in Standard Mode
Bulk and Interrupt transactions are managed in the same way.
Figure 16-9. Bulk/Interrupt OUT transactions in Standard Mode
An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt
packets.
When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB con-
troller. This triggers an interrupt if enabled. The firmware has to select the corresponding
endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet
is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be
read.
When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit
to allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0
bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each
OUT requests.
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct and the
endpoint Byte counter contains the number of Bytes sent by the Host.
OUT
OUT
OUT
OUT
HOST
DATA0 (n Bytes)
DATA1
DATA1
DATA1
ACK
NAK
NAK
ACK
UFI
RXOUTB0
RXOUTB0
Endpoint FIFO Read Byte 1
Endpoint FIFO Read Byte 2
Endpoint FIFO Read Byte n
Endpoint FIFO Read Byte 1
Clear RXOUTB0
C51
4341H–MP3–10/07