AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 90

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

15.1.7
15.1.8
90
AT8xC51SND2C/MP3B
Digital Mixer Control
Master Clock and Sampling Frequency Selection
The Audio DAC features a digital mixer that allows the mixing and selection of multiple input
sources.
The mixing / multiplexing functions are described in the following table according with the next
figure:
Figure 15-9. Mixing / Multiplexing functions
Note:
Note:
The following table describes the different modes available for master clock and sampling fre-
quency selection by setting OVRSEL bit in DAC_CSFC register (refer to Table 15-21.).
Table 15-7.
The selection of input sample size is done using the NBITS 1:0 in DAC_MISC register (refer to
Table 15-22.) according to Table 15-8.
Table 15-8.
Signal
LMSMIN1
LMSMIN2
RMSMIN1
RMSMIN2
Whenever the two mixer inputs are selected, a –6 dB gain is applied to the output signal. When-
ever only one input is selected, no gain is applied.
Refer to DAC_MC register Table 15-20. for signal description
To DACs
Master Clock selection
Input Sample Size Selection
OVRSEL
Description
Left Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to disable
Left Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to disable
Right Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to disable
Right Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to disable
NBITS 1:0
0
1
00
01
10
Volume
Volume
Control
Control
Right channel
Left channel
+
+
2
1
1
2
Volume
Volume
Control
Control
Master Clock
256 x FS
384 x FS
Format
16 bits
18 bits
20 bits
From digital
filters
4341H–MP3–10/07