AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 9

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

4341H–MP3–10/07
Table 4-11.
Table 4-12.
Note:
Table 4-13.
ADCREFP
ADCREFN
Signal
Signal
Name
AD7:0
Name
A15:8
EA
RST
ALE
TST
WR
Signal
AIN1:0
ISP
RD
Name
(1)
1. For ROM/Flash/ROMless Dice product versions only.
Type
Type
I/O
I/O
I/O
O
O
O
I
I
I
A/D Converter Signal Description (
Type
External Access Signal Description
System Signal Description
I
I
I
Description
Address Lines
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the IDE
interface.
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid address
information is available on lines A7:0. An external latch is used to demultiplex
the address from address/data bus.
ISP Enable Input (AT89C51SND2C Only)
This signal must be held to GND through a pull-down resistor at the falling
reset to force execution of the internal bootloader.
Read Signal
Read signal asserted during external data memory read operation.
Write Signal
Write signal asserted during external data memory write operation.
External Access Enable: EA must be externally held low to enable the device
to fetch code from external program memory locations 0000H to FFFFH (RD).
Description
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than V
This pin has an internal pull-down resistor which allows the device to be reset
by connecting a capacitor between this pin and V
Asserting RST when the chip is in Idle mode or Power-Down mode returns the
chip to normal operation.
Test Input
Test mode entry signal. This pin must be set to V
Description
A/D Analog Inputs
Analog Positive Voltage Reference Input
Analog Negative Voltage Reference Input
IL
is applied, whether or not the oscillator is running.
AT8XSND2CMP3B
AT8xC51SND2C/MP3B
DD
DD
.
.
only)
Alternate
Alternate
Alternate
Function
Function
Function
P2.7:0
P0.7:0
P3.7
P3.6
-
-
-
-
-
-
-
-
9