AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 48

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

10.1.2
10.1.3
10.2
48
Reset Recommendation to Prevent Flash Corruption
AT8xC51SND2C/MP3B
Warm Reset
Watchdog Reset
To determine the capacitor value to implement, the highest value of these 2 parameters has to
be chosen.
different oscillator startup and V
Table 10-2.
Note:
To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24
oscillator clock periods) while the oscillator is running. The number of clock periods is mode
independent (X2 or X1).
As detailed in section “Watchdog Timer”, page 60, the WDT generates a 96-clock period pulse
on the RST pin. In order to properly propagate this pulse to the rest of the application in case of
external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be added as shown in
Figure 10-2.
Figure 10-2. Reset Circuitry for WDT Reset-out Usage
An example of bad initialization situation may occur in an instance where the bit ENBOOT in
AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows map-
ping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet due to a
bad reset) the bit ENBOOT in SFRs may be set. If the value of Program Counter is accidently in
the range of the boot memory addresses then a Flash access (write or erase) may corrupt the
Flash on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to prevent
system malfunction during periods of insufficient power supply voltage (power supply failure,
power supply switched off).
Start-Up Time
Oscillator
1. These values assume V
20 ms
5 ms
sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged,
leading to a bad reset sequence.
Table 10-2
VDD
VDD
VSS
+
Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor
RST
gives some capacitor values examples for a minimum R
1K
DD
820 nF
2.7 µF
1 ms
DD
rise times.
RST
starts from 0V to the nominal value. If the time between 2 on/off
VDD
VSS
P
VDD Rise Time
10 ms
1.2 µF
3.9 µF
From WDT
Reset Source
To CPU Core
and Peripherals
To Other
On-board
Circuitry
(1)
RST
100 ms
12 µF
12 µF
4341H–MP3–10/07
of 50 KΩ and