AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 113

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

16.6.4
4341H–MP3–10/07
Bulk/Interrupt IN Transactions in Ping-pong Mode
Figure 16-12. Bulk/Interrupt IN transactions in Ping-pong mode
An endpoint should be first enabled and configured before being able to send Bulk or Interrupt
packets.
The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN
request concerning the endpoint. The FIFO banks are automatically switched, and the firmware
can immediately write into the endpoint FIFO bank 1.
When the IN packet concerning the bank 0 has been sent and acknowledged by the Host, the
TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
should clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO
banks are then automatically switched.
When the IN packet concerning the bank 1 has been sent and acknowledged by the Host, the
TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware
should clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by the firm-
ware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller
will answer a NAK handshake for each IN requests concerning this bank.
Note that in the example above, the firmware clears the Transmit Complete bit (TXCBulk-out-
MPL) before setting the Transmit Ready bit (TXRDY). This is done in order to avoid the firmware
to clear at the same time the TXCMPL bit for for bank 0 and the bank 1.
The firmware should never write more Bytes than supported by the endpoint FIFO.
HOST
IN
IN
IN
IN
ACK
ACK
ACK
DATA0 (n Bytes)
DATA1 (m Bytes)
DATA0 (p Bytes)
NACK
UFI
TXCMPL
TXCMPL
AT8xC51SND2C/MP3B
Endpoint FIFO bank 0 - Write Byte 1
Endpoint FIFO bank 0 - Write Byte 2
Endpoint FIFO bank 0 - Write Byte n
Endpoint FIFO bank 1 - Write Byte 1
Endpoint FIFO bank 1 - Write Byte 2
Endpoint FIFO bank 1 - Write Byte m
Endpoint FIFO bank 0 - Write Byte 1
Endpoint FIFO bank 0 - Write Byte 2
Endpoint FIFO bank 0 - Write Byte p
Endpoint FIFO bank 1 - Write Byte 1
C51
Clear TXCMPL
Clear TXCMPL
Set TXRDY
Set TXRDY
Set TXRDY
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