AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 169

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

20.2.2
20.3
4341H–MP3–10/07
Synchronous Mode (Mode 0)
Internal Baud Rate Generator
Figure 20-1. Timer 1 Baud Rate Generator Block Diagram
When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the
timer. As shown in Figure 20-2 the Internal Baud Rate Generator is an 8-bit auto-reload timer
fed by the peripheral clock or by the peripheral clock divided by 6 depending on the SPD bit in
BDRCON register (see Table 20-7). The Internal Baud Rate Generator is enabled by setting
BBR bit in BDRCON register. SMOD1 bit in PCON register allows doubling of the generated
baud rate.
Figure 20-2. Internal Baud Rate Generator Block Diagram
Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0 capabil-
ities of a device with shift registers. The transmit data (TXD) pin outputs a set of eight clock
pulses while the receive data (RXD) pin transmits or receives a Byte of data. The 8-bit data are
transmitted and received least-significant bit (LSB) first. Shifts occur at a fixed Baud Rate (see
Section "Baud Rate Selection (Mode 0)", page 171). Figure 20-3 shows the serial port block dia-
gram in Mode 0.
CLOCK
CLOCK
INT1
PER
PER
T1
GATE1
TMOD.7
TCON.6
TR1
÷ 6
÷ 6
BDRCON.1
SPD
TMOD.6
C/T1#
0
1
0
1
BDRCON.4
BRR
AT8xC51SND2C/MP3B
(8 bits)
(8 bits)
(8 bits)
(8 bits)
BRG
BRL
TH1
TL1
Overflow
Overflow
To serial
Port (M0)
CLOCK
IBRG0
÷ 2
÷ 2
SMOD1
SMOD1
PCON.7
CLOCK
PCON.7
CLOCK
IBRG
T1
0
1
0
1
To serial
Port
To serial
Port
169