AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 27

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

7.3
7.3.1
4341H–MP3–10/07
Dual Data Pointer
Description
in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode,
refer to the Section “X2 Feature”, page 14.
Slow peripherals can be accessed by stretching the read and write cycles. This is done using the
M0 bit in AUXR register. Setting this bit changes the width of the RD and WR signals from 3 to
15 CPU clock periods.
For simplicity,
do not provide precise timing information. For bus cycle timing parameters refer to the Section
“AC Characteristics”.
Figure 7-4.
Notes:
Figure 7-5.
Notes:
The AT8xC51SND2C implement a second data pointer for speeding up code execution and
reducing code size in case of intensive usage of external memory accesses.
CPU Clock
1.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 out-
1.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 out-
CPU Clock
RD
puts SFR content instead of DPH.
WR
puts SFR content instead of DPH.
RD
ALE
WR
signal may be stretched using M0 bit in AUXR register.
External Data Read Waveforms
External Data Write Waveforms
Figure 7-4
P0
P2
ALE
signal may be stretched using M0 bit in AUXR register.
(1)
P0
P2
(1)
P2
P2
and
Figure 7-5
DPL or Ri
DPL or Ri
depict the bus cycle waveforms in idealized form and
AT8xC51SND2C/MP3B
DPH or P2
DPH or P2
(2),(3)
(2),(3)
D7:0
D7:0
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