AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 64

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

13.1.2
13.1.3
64
AT8xC51SND2C/MP3B
MP3 Data
MP3 Clock
The MP3 decoder does not start any frame decoding before having a complete frame in its input
buffer
consisting of data request and data acknowledgment is implemented. Each time the MP3
decoder needs MP3 data, it sets the MPREQ, MPFREQ and MPBREQ flags respectively in
MP3STA and MP3STA1 registers. MPREQ flag can generate an interrupt if enabled as
explained in Section “Interrupt”. The CPU must then load data in the buffer by writing it through
MP3DAT register thus acknowledging the previous request. As shown in Figure 13-2, the
MPFREQ flag remains set while data (i.e a frame) is requested by the decoder. It is cleared
when no more data is requested and set again when new data are requested. MPBREQ flag
toggles at every Byte writing.
Note:
Figure 13-2. Data Timing Diagram
The MP3 decoder clock is generated by division of the PLL clock. The division factor is given by
MPCD4:0 bits in MP3CLK register. Figure 13-3 shows the MP3 decoder clock generator and its
calculation formula. The MP3 decoder clock frequency depends only on the incoming MP3
frames.
Figure 13-3. MP3 Clock Generator and Symbol
As soon as the frame header has been decoded and the MPEG version extracted, the minimum
MP3 input frequency must be programmed according to Table 13-1.
Table 13-1.
(1)
. In order to manage the load of MP3 data in the frame buffer, a hardware handshake
Write to MP3DAT
1. The first request after enable, consists in 1024 Bytes of data to fill in the input buffer.
MPBREQ Flag
MPFREQ Flag
CLOCK
MPREQ Flag
PLL
MP3 Clock Frequency
MPEG Version
II
I
Cleared when Reading MP3STA
MPCD4:0
MP3CLK
MP3clk
MP3 Decoder Clock
=
----------------------------
MPCD
PLLclk
+
1
Minimum MP3 Clock (MHz)
10.5
21
MP3 Clock Symbol
CLOCK
MP3
4341H–MP3–10/07