AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 20

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

6.2.3
6.2.4
6.3
6.4
6.4.1
20
Hardware Security System
Boot Memory Execution
AT8xC51SND2C/MP3B
Hardware Security Space
Extra Row Space
Software Boot Mapping
This space is composed of one Byte: the Hardware Security Byte (HSB see Table 6-3) divided in
2 separate nibbles. The MSN contains the X2 mode configuration bit and the Boot Loader Jump
Bit as detailed in Section “Boot Memory Execution”, page 20 and can be written by software
while the LSN contains the lock system level to protect the memory content against piracy as
detailed in Section “Hardware Security System”, page 20 and can only be written by hardware.
This space is composed of 2 Bytes:
•
•
The AT89C51SND2C implements three lock bits LB2:0 in the LSN of HSB (see Table 6-3) pro-
viding three levels of security for user’s program as described in
AT83SND2C is always set in read disabled mode.
Level 0 is the level of an erased part and does not enable any security feature.
Level 1 locks the hardware programming of both user and boot memories.
Level 2 locks also hardware verifying of both user and boot memories
Level 3 locks also the external execution.
Table 6-1.
Notes:
As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented to allow
boot memory to be mapped in the code space for execution at addresses from F000h to FFFFh.
The boot memory is enabled by setting the ENBOOT bit in AUXR1 (see Figure 6-2). The three
ways to set this bit are detailed in the following sections.
The software way to set ENBOOT consists in writing to AUXR1 from the user’s software. This
enables boot loader or API routines execution.
Level
3
0
1
2
(3)
The Software Boot Vector (SBV, see Table 6-4).
This Byte is used by the software boot loader to build the boot address.
The Software Security Byte (SSB, see
This Byte is used to lock the execution of some boot loader commands.
1. U means unprogrammed, P means programmed and X means don’t care (programmed or
2. AT89C51SND2C products are delivered with third level programmed to ensure that the code
LB2
U
U
U
P
unprogrammed).
programmed by software using ISP or user’s boot loader is secured from any hardware piracy.
Lock Bit Features
LB1
U
U
P
X
LB0
U
P
X
X
Execution
Internal
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(1)
Execution
External
Table
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6-5).
Hardware
Verifying
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Programming
Hardware
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Table 6-1
4341H–MP3–10/07
Programming
Software
while the
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