AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 146

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

Figure 18-17. Data Block Transmission Flows
18.6.4
18.6.4.1
18.6.4.2
146
AT8xC51SND2C/MP3B
Data Receiver
Configuration
Data Reception
write 16 data to MMDAT
write 8 data to MMDAT
a. Polling mode
Start Transmission
F1EI or F2EI = 1?
Transmission
No More Data
FIFO Empty?
FIFOs Filling
Data Block
FIFO Filling
DATEN = 1
DATEN = 0
To Send?
To receive data from the card you must first configure the data controller in reception mode by
clearing the DATDIR bit in MMCON1 register.
Figure 18-18 summarizes the data stream reception flows in both polling and interrupt modes
while Figure 18-19 summarizes the data block reception flows in both polling and interrupt
modes, these flows assume that block length is greater than 16 Bytes.
The end of a data frame (block or stream) reception is signalled to you by the EOFI flag in
MMINT register. This flag may generate an MMC interrupt request as detailed in Section "Inter-
rupt", page 148. When this flag is set, 2 other flags in MMSTA register: DATFS and CRC16S
give a status on the frame received. DATFS indicates if the frame format is correct or not: a valid
End bit has been received, and CRC16S indicates if the CRC16 computation is correct or not. In
case of data stream CRC16S has no meaning and stays cleared.
According to the MMC specification data transmission from the card starts after the access time
delay (formally N
locking of the MMC controller when card does not send its data (e.g. physically removed from
the bus), you must launch a time-out period to exit from such situation. In case of time-out you
AC
parameter) beginning from the End bit of the read command. To avoid any
write 16 data to MMDAT
Unmask FIFOs Empty
Start Transmission
Initialization
FIFOs Filling
Data Block
DATEN = 1
DATEN = 0
F1EM = 0
F2EM = 0
b. Interrupt mode
write 8 data to MMDAT
Transmission ISR
Mask FIFOs Empty
F1EI or F2EI = 1?
No More Data
FIFO Empty?
Data Block
FIFO Filling
To Send?
F1EM = 1
F2EM = 1
4341H–MP3–10/07