AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 151

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

4341H–MP3–10/07
Table 18-9.
MMCON1 (S:E5h) – MMC Control Register 1
Reset Value = 0000 0000b
Table 18-10. MMCON2 Register
MMCON2 (S:E6h) – MMC Control Register 2
Reset Value = 0000 0000b
Bit Number
Bit Number
MMCEN
BLEN3
7 - 4
4-3
2-1
7
3
2
1
0
7
7
6
5
0
Mnemonic
Mnemonic
RESPEN
DATD1:0
BLEN3:0
MMCEN
MMCON1 Register
DATDIR
CMDEN
FLOWC
BLEN2
DATEN
DCR
DCR
CCR
Bit
Bit
6
6
-
Description
Block Length Bits
Refer to Table 18-7 for bits description. Do not program value > 1011b
Data Direction Bit
Set to select data transfer from host to card (write mode).
Clear to select data transfer from card to host (read mode).
Data Transmission Enable Bit
Set and clear to enable data transmission immediately or after response has been
received.
Response Enable Bit
Set and clear to enable the reception of a response following a command transmission.
Description
MMC Clock Enable Bit
Set to enable the MCLK clocks and activate the MMC controller.
Clear to disable the MMC clocks and freeze the MMC controller.
Data Controller Reset Bit
Set and clear to reset the data line controller in case of transfer abort.
Command Controller Reset Bit
Set and clear to reset the command line controller in case of transfer abort.
Reserved
The value read from these bits is always 0. Do not set these bits.
Used to delay the data transmission after a response from 3 MMC clock periods (all bits
cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock periods.
MMC Flow Control Bit
Set to enable the flow control during data transfers.
Clear to disable the flow control during data transfers.
Command Transmission Enable Bit
Set and clear to enable transmission of the command FIFO to the card.
Data Transmission Delay Bits
BLEN1
CCR
5
5
BLEN0
4
4
-
DATDIR
AT8xC51SND2C/MP3B
3
3
-
DATEN
DATD1
2
2
RESPEN
DATD0
1
1
CMDEN
FLOWC
0
0
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