AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 130
![IC 8051 MCU FLASH 64K MP3 100BGA](/photos/12/43/124396/313-100-bga_sml.jpg)
AT89C51SND2C-7FTUL
Manufacturer Part Number
AT89C51SND2C-7FTUL
Description
IC 8051 MCU FLASH 64K MP3 100BGA
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51SND2C-7FTUL.pdf
(242 pages)
Specifications of AT89C51SND2C-7FTUL
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b; D/A 2x20b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
ATAPI, I2S, IDE, SPI, UART, USB
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT89C51SND2C7FTUL
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51SND2C-7FTUL
Manufacturer:
ATMEL
Quantity:
4 371
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AT8xC51SND2C/MP3B
Table 16-15. UFNUMH Register
Reset Value = 00h
Table 16-16. USBCLK Register
Reset Value = 0000 0000b
Bit Number
Bit Number
7 - 3
7 - 2
1 - 0
2-0
7
5
4
3
7
-
-
Mnemonic
Mnemonic
FNUM10:8
USBCD1:0
CRCERR
UFNUMH (S:BBh, Read-only) – USB Frame Number High Register
CRCOK
USBCLK (S:EAh) – USB Clock Divider Register
Bit
Bit
6
6
-
-
-
-
-
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
Frame Number CRC OK Bit
Set by hardware after a non corrupted Frame Number in Start of Frame Packet is
received.
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
Frame Number CRC Error Bit
Set by hardware after a corrupted Frame Number in Start of Frame Packet is received.
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
Reserved
The value read from this bits is always 0. Do not set this bit.
Frame Number
Upper 3 bits of the 11-bit Frame Number. It is provided in the last received SOF packet.
FNUM does not change if a corrupted SOF is received.
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
USB Controller Clock Divider
2-bit divider for USB controller clock generation.
CRCOK
5
5
-
CRCERR
4
4
-
3
3
-
-
FNUM10
2
2
-
USBCD1
FNUM9
1
1
4341H–MP3–10/07
USBCD0
FNUM8
0
0
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