AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 124

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

124
AT8xC51SND2C/MP3B
Table 16-6.
Reset Value = 0001 0000b
Table 16-7.
Reset Value = 0000 0000b
Bit Number
Bit Number
7 - 6
2 - 1
7 - 2
1 - 0
7
5
4
3
0
7
-
-
EWUPCPU
Mnemonic
Mnemonic
EPNUM1:0
EEOFINT
ESOFINT
USBIEN Register
USBIEN (S:BEh) – USB Global Interrupt Enable Register
ESPINT
UEPNUM Register
UEPNUM (S:C7h) – USB Endpoint Number
Bit
Bit
6
6
-
-
-
-
-
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt Enable Bit
Set to enable the Wake Up CPU interrupt.
Clear to disable the Wake Up CPU interrupt.
End Of Reset Interrupt Enable Bit
Set to enable the End Of Reset interrupt. This bit is set after reset.
Clear to disable End Of Reset interrupt.
Start Of Frame Interrupt Enable Bit
Set to enable the SOF interrupt.
Clear to disable the SOF interrupt.
Reserved
The value read from these bits is always 0. Do not set these bits.
Suspend Interrupt Enable Bit
Set to enable Suspend interrupt.
Clear to disable Suspend interrupt.
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
Endpoint Number Bits
Set this field with the number of the endpoint which should be accessed when reading or
writing to registers UEPSTAX, UEPDATX, UBYCTX or UEPCONX.
EWUPCPU
5
5
-
EEORINT
4
4
-
ESOFINT
3
3
-
2
2
-
-
EPNUM1
1
1
-
4341H–MP3–10/07
EPNUM0
ESPINT
0
0