AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 138

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

18.2.5
138
AT8xC51SND2C/MP3B
Data Packet Format
Table 18-2.
Table 18-3.
Table 18-4.
Table 18-5.
Table 18-6.
There are 2 types of data packets: stream and block. As shown in Figure 18-8, stream data
packets have an indeterminate length while block packets have a fixed length depending on the
block length. Each data packet is preceded by a Start bit: a low level on MCMD line and suc-
ceeded by an End bit: a high level on MCMD line. Due to the fact that there is no predefined end
in stream packets, CRC protection is not included in this case. The CRC protection algorithm for
block data is a 16-bit CCITT polynomial.
Bit Position
Description
Bit Position
Bit Position
Description
Bit Position
Width (bits)
Width (bits)
Description
Width (bits)
Width (bits)
Description
Bit Position
Description
Width (bits)
Value
Value
Value
Value
Value
R1 Response Format (Normal Response)
R2 Response Format (CID and CSD registers)
R3 Response Format (OCR Register)
R4 Response Format (Fast I/O)
R5 Response Format
Start bit
Start bit
Start bit
Start bit
47
‘0’
47
‘0’
1
47
1
‘0’
47
‘0’
1
1
Start bit
135
‘0’
1
Transmission bit
Transmission bit
Transmission bit
Transmission bit
46
‘0’
46
1
‘0’
1
46
‘0’
1
46
‘0’
Transmission bit
1
134
‘0’
1
Command
Reserved
Command
Command
‘101000’
‘111111’
‘100111’
[45:40]
[45:40]
[45:40]
Index
45:40
Index
Index
6
6
6
6
-
[133:128]
Reserved
‘111111’
6
OCR register
Card Status
Argument
Argument
[39:8]
[39:8]
[39:8]
39:8
32
32
32
32
-
-
-
-
Argument
[127:1]
32
Reserved
-
‘1111111’
CRC7
CRC7
CRC7
[7:1]
[7:1]
[7:1]
7:1
7
7
7
-
7
-
-
4341H–MP3–10/07
End bit
End bit
End bit
End bit
End bit
‘1’
0
1
‘1’
‘1’
‘1’
‘1’
0
1
0
1
0
1
0
1