AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 158

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

Figure 19-4. SPI Slave Mode Block Diagram
Note:
19.1.3
19.1.4
158
1. MSTR bit in SPCON is cleared to select slave mode.
AT8xC51SND2C/MP3B
Bit Rate
Data Transfer
MISO/P4.2
MOSI/P4.1
SCK/P4.2
SS/P4.3
When the AT8xC51SND2C is the only slave on the bus, it can be useful not to use SS# pin and
get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no
effect when CPHA is cleared (see Section "SS Management", page 159).
The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and SPR0
control bits in SPCON according to Table 19-1. These bit rates are derived from the peripheral
clock (F
Table 19-1.
Notes:
The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle state
the Clock Phase bit (CPHA in SPCON) defines the edges on which the input data are sampled
and the edges on which the output data are shifted (see Figure 19-5 and Figure 19-6). The SI
signal is output from the selected slave and the SO signal is the output from the master. The
AT8xC51SND2C captures data from the SI line while the selected slave captures data from the
SO line.
SPR2
0
0
0
0
1
1
1
1
PER
1. These frequencies are achieved in X1 mode, F
2. These frequencies are achieved in X2 mode, F
SPR1
0
0
1
1
0
0
1
1
) issued from the Clock Controller block as detailed in Section "Oscillator", page 13.
SPCON.5
SSDIS
Serial Bit Rates
SPR0
0
1
0
1
0
1
0
1
Control and Clock Logic
6 MHz
46.875
187.5
93.75
3000
1500
6000
SPCON.2
750
375
CPHA
(1)
8 MHz
4000
2000
1000
8000
62.5
500
250
125
SPCON.3
CPOL
(1)
10 MHz
Bit Rate (kHz) Vs F
156.25
78.125
10000
312.5
5000
2500
1250
625
(1)
I
SPSTA.7
SPIF
12 MHz
8-bit Shift Register
PER
PER
12000
187.5
93.75
6000
3000
1500
750
375
SPDAT RD
SPDAT WR
= F
= F
(2)
PER
OSC
OSC
16 MHz
.
÷ 2.
16000
8000
4000
2000
1000
500
250
125
(2)
Q
20 MHz
156.25
10000
20000
312.5
5000
2500
1250
625
(2)
4341H–MP3–10/07
F
PER
128
Divider
16
32
64
(1)
2
4
8
1
while