AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 141

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

Figure 18-12. Command Line Controller Block Diagram
18.5.1
4341H–MP3–10/07
Command Transmitter
Command Transmitter
Command Receiver
TX Pointer
RX Pointer
MMCON0.4
MMCON0.5
CRPTR
CTPTR
For sending a command to the card, user must load the command index (1 Byte) and argument
(4 Bytes) in the command transmit FIFO using the MMCMD register. Before starting transmis-
sion by setting and clearing the CMDEN bit in MMCON1 register, user must first configure:
•
•
•
Figure 18-13 summarizes the command transmission flow.
As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicating that
write to the FIFO is locked. This mechanism is implemented to avoid command overrun.
The end of the command transmission is signalled to you by the EOCI flag in MMINT register
becoming set. This flag may generate an MMC interrupt request as detailed in Section "Inter-
rupt", page 148. The end of the command transmission also resets the CFLCK flag.
User may abort command loading by setting and clearing the CTPTR bit in MMCON0 register
which resets the write pointer to the transmit FIFO.
17 - Byte FIFO
5-Byte FIFO
MMCMD
MMCMD
RESPEN bit in MMCON1 register to indicate whether a response is expected or not.
RFMT bit in MMCON0 register to indicate the response size expected.
CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the response will
be computed or not. In order to avoid CRC error, CRCDIS may be set for response that do
not include CRC7.
MMSTA.0
CFLCK
Write
Read
MMCON1.0
Data Converter
CMDEN
Data Converter
RESPEN
MMCON1.1
// -> Serial
Serial -> //
Finished State Machine
Finished State Machine
RX COMMAND Line
TX COMMAND Line
MMCON0.1
RFMT
MMSTA.2
CRC7S
CRC7 and Format
MMCON0.0
Generator
CRCDIS
CRC7
Checker
RESPFS
MMSTA.1
AT8xC51SND2C/MP3B
MMINT.5
MMINT.6
EOCI
EORI
MCMD
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