AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 182

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

Figure 21-2. Complete Data Transfer on TWI Bus
21.1.1
182
AT8xC51SND2C/MP3B
Bit Rate
SDA
SCL
S
The four operating modes are:
•
•
•
•
Data transfer in each mode of operation are shown in Figure 21-3 through Figure 21-6. These
figures contain the following abbreviations:
A
A
Data
S
P
MR
MT
SLA
GCA
R
W
In Figure 21-3 through Figure 21-6, circles are used to indicate when the serial interrupt flag is
set. The numbers in the circles show the status code held in SSSTA. At these points, a service
routine must be executed to continue or complete the serial transfer. These service routines are
not critical since the serial transfer is suspended until the serial interrupt flag is cleared by
software.
When the serial interrupt routine is entered, the status code in SSSTA is used to branch to the
appropriate service routine. For each status code, the required software action and details of the
following serial transfer are given in Table 21-2 through Table 21-6.
The bit rate can be selected from seven predefined bit rates or from a programmable bit rate
generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 21-9). The
predefined bit rates are derived from the peripheral clock (F
block as detailed in section "Oscillator", page 13, while bit rate generator is based on timer 1
overflow output.
MSB
1
Master transmitter
Master receiver
Slave transmitter
Slave receiver
Slave Address
2
Acknowledge bit (low level at SDA)
Not acknowledge bit (high level on SDA)
8-bit data Byte
START condition
STOP condition
Master Receive
Master Transmit
Slave Address
General Call Address (00h)
Read bit (high level at SDA)
Write bit (low level at SDA)
direction
R/W
bit
8
receiver
signal
ACK
from
9
Clock Line Held Low While Serial Interrupts Are Serviced
1
Nth data Byte
2
PER
) issued from the Clock Controller
8
receiver
signal
ACK
from
9
P/S
4341H–MP3–10/07