AT89C51SND2C-7FTUL Atmel, AT89C51SND2C-7FTUL Datasheet - Page 143

• Manufacturer Part Number: AT89C51SND2C-7FTUL
• Description: IC 8051 MCU FLASH 64K MP3 100BGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND2C-7FTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b; D/A 2x20b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: ATAPI, I2S, IDE, SPI, UART, USB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C51SND2C7FTUL

Figure 18-14. Data Line Controller Block Diagram
18.6.1
18.6.2
4341H–MP3–10/07
RX Pointer
TX Pointer
MMCON0.6
MMCON0.7
FIFO Implementation
Data Configuration
DTPTR
DRPTR
MMINT.0
MMINT.1
F1EI
F2EI
16-Byte FIFO
The 16-Byte FIFO is based on a dual 8-Byte FIFOs managed using 2 pointers and four flags
indicating the status full and empty of each FIFO.
Pointers are not accessible to user but can be reset at any time by setting and clearing DRPTR
and DTPTR bits in MMCON0 register. Resetting the pointers is equivalent to abort the writing or
reading of data.
F1EI and F2EI flags in MMINT register signal when set that respectively FIFO1 and FIFO2 are
empty. F1FI and F2FI flags in MMINT register signal when set that respectively FIFO1 and
FIFO2 are full. These flags may generate an MMC interrupt request as detailed in
Section “Interrupt”.
Before sending or receiving any data, the data line controller must be configured according to
the type of the data transfer considered. This is achieved using the Data Format bit: DFMT in
MMCON0 register. Clearing DFMT bit enables the data stream format while setting DFMT bit
enables the data block format. In data block format, user must also configure the single or multi-
block mode by clearing or setting the MBLOCK bit in MMCON0 register and the block length
using BLEN3:0 bits in MMCON1 according to Table 18-7. Figure 18-15 summarizes the data
modes configuration flows.
Table 18-7.
MMDAT
FIFO 1
FIFO 2
8-Byte
8-Byte
MMINT.2
MMINT.3
F1FI
F2FI
BLEN = 0000 to 1011
Block Length Programming
BLEN3:0
> 1011
MMCON0.2
CRC16 and Format
DFMT
MMSTA.3
DATFS
MMINT.1
MCBI
Data Converter
Checker
// -> Serial
MBLOCK
MMCON0.3
CRC16S
MMSTA.4
CBUSY
MMSTA.5
Finished State Machine
Block Length (Byte)
Length = 2
Reserved: do not program BLEN3:0 > 1011
DATA Line
MMCON1.2
DATEN
BLEN
Data Converter
Serial -> //
: 1 to 2048
Generator
MMCON1.3
DATDIR
CRC16
AT8xC51SND2C/MP3B
MMCON1.7:4
BLEN3:0
MMINT.4
EOFI
MDAT
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